Frequency divider circuit



Ap 1949. c. E. HALLMARK 2,467,476

FREQUENCY DIVIDER CIRCUIT Filed Oct. 17, 1945 FIG.2

INVENTOR CLYDE E. HALLMARK ATTORNEY Patented Apr. 19, 1949 UNITED STATES PATENT OFFICE FREQUENCY DIVIDER CIRCUIT Application October 17, 1945, Serial No. 622,730

This invention relates to frequency divider circults, and more particularly relates to a pulse operated electrical counter circuit arranged for developing output pulses at a frequency which is a submultiple of that of the input pulses.

Frequency divider circuits find wide application whenever it is desired to develop an output signal at a subharmonic of the frequency of an input signal. Frequency divider circuits or electrical counters are used, for example, in the timing unit of a television transmitter. A television timing unit is arranged to develop control signals such as blanking and synchronizing pulses recurring at the line and field frequencies. The line or horizontal synchronizing signal and the field or vertical synchronizing signal have a frequency of, for example, 15,750 cycles per second and of 60 cycles per second, respectively, in accordance with the present standards adopted by the Radio Manufacturers Association. In the timing unit of a television transmitter, waves at a frequency of 15,750 cycles are developed which must be synchronized with the 60 cycle power input. To this end the frequency of 15,750 cycles is doubled and then divided to derive a 60 cycle output signal which is compared with the 60 cycle input power supply by means of a frequency correction circuit. Thus, the vertical and horizontal synchronizing signals are synchronized at all times.

The frequency divider circuit forming part of a television timing unit conventionally comprises a chain of, for example, four multivibrators each being associated with an insulating amplifier stage. A circuit of this type is reliable in its operation but is comparatively complicated and requires a large number of amplifier tubes as well as a considerable number of frequency divider stages. Another drawback of a conventional counter circuit comprising a chain of multivibrators is that each multivibrator must be tuned or adjusted to oscillate at a predetermined frequency.

It is an object of the present invention, therefore, to provide a frequency divider circuit that is simpler than prior art frequency dividers and permits a substantial count-down ratio of the frequency of the input pulses compared to the frequency of the output pulses.

Another object of the invention is to provide an electrical counter circuit which need not be tuned or adjusted to the fundamental frequency to be divided or a subharmonic thereof, and which will permit, therefore, to derive output pulses at a subharmonic of the frequency of the input pulses in any frequency range.

7 Claims. (Cl. 172-281) A further object of the invention is to provide a frequency divider circuit comprising a plurality of gas diodes of the cold cathode type.

In accordance with the present invention, there is provided a frequency divider circuit comprising a plurality of unilaterally conducting devices of predetermined breakdown voltage and connected in series. A plurality of storage condensers are provided each of which is connected in shunt between a fixed reference potential source and the input of one of the unilaterally conducting devices. Means are provided for applying spaced pulses of a predetermined voltage across the first storage condenser. The capacitances of the storage condensers increase progressively from the first to the last condenser so that each of the unilaterally conducting devices is rendered conducting when the condenser in its input circuit has reached the predetermined breakdown voltage with respect to the reference potential. Finally, means are provided for deriving output pulses at a submultiple of the frequency of the input pulses.

For a better understanding of the invention, together with other and further objects thereof, reference is made to the following description, taken in connection with the accompanying drawing, and its scope will be pointed out in the appended claims.

In the accompanying drawing, Fig. 1 is a circuit diagram of a frequency divider circuit embodying the present invention, while Fig. 2 is a circuit diagram of a modified frequency divider circuit in accordance with the invention.

Referring now more particularly to Fig. 1 of the drawing, there is provided a frequency divider circuit comprising three unilaterally conducting devices l, 2 and 3 connected in series. Unilaterally-conducting devices I, 2 and 3 have a predetermined break-down voltage and preferably are gas diodes of the cold cathode type such, for example, as neon lamps. Three storage condensers 4, 5 and 6 are individually connected in shunt between ground, as indicated, and the input of diodes I, 2 and 3, respectively. Load resistor l is connected between ground and the output of gas diode 3 for developing the output signal which may be obtained from terminals l0.

Means are provided for applying spaced pulses of positive voltage across the first storage condenser t. To this end there has been illustrated a conventional circuit comprising pulse generator ll connected to amplifier tube l2. Amplifier tube l2 may be a triode as illustrated or a pentode. Amplifier tube I2 comprises cathode l3 which is grounded as shown, control grid I4 connected to pulse generator II and anode I5. Pulse enerator II develops voltage pulses of negative polarity with respect to ground, as illustrated at I6. Amplifier I2 is arranged to be normally conducting. However, when a pulse I6 of negative polarity is developed by pulse generator II and impressed upon control grid I4, the space current in amplifier I2 terminates. Anode I is connected to anode supply B+ through anode resistor II.

One terminal of charging condenser 20 is connected to anode I5. The other terminal of condenser 20 is connected to the anode of high vacuum diode 2I and the cathode of high vacuum diode 22, both diodes being arranged in parallel. The cathode of high vacuum diode 2I is connected to the input of gas diode I and to storage condenser 4, while the anode of high vacuum diode 22 is connected to ground.

The frequency divider circuit illustrated in Fig. 1 operates as follows. It may be assumed that initially condensers 20, 4, 5 and 6 are all discharged. Amplifier tube I2 is arranged to be normally conducting, as pointed out hereinabove. Accordingly, the space current flowing through anode resistor II develops a voltage drop thereacross which is impressed upon charging condenser 20. Upon the arrival of a negative pulse I6 of sumcient amplitude on control grid I4, amplifier I2 ceases to conduct space current. Consequently, the voltage impressed upon charging condenser 20 is now equal to anode supply voltage B+ because no current flows through anode resistor IT. The positive voltage pulses developed across anode resistor H are indicated at I8.

High vacuum diode 2I now begins to conduct space current until the charge remaining on charging condenser 20 equals that of storage condenser 4. Upon the termination of a pulse I6, amplifier I2 again begins to conduct space current whereupon the voltage applied to charging condenser 20 is reduced. Charging condenser 20 is now discharged through high vacuum diode 22 and amplifier I2 connected in series. The right hand terminal of condenser 20 connected to high vacuum diodes 2| and 22 is brought substantially to ground potential.

It will be seen that each time a pulse I6 is impressed upon control grid I4 a certain charge is applied to storage condenser 4 through charging condenser 20. The charg applied to charging condenser 20 and storage condenser 4 is independent from the amplitude of input pulses I6 as long as the pulses are able to swing control grid I4 sufficiently negative to interrupt space current fiowing through amplifier tube I2. The voltage impressed upon charging condenser 20 depends primarily upon the voltage of the anode supply B+.

Each gas diode I, 2 and 3 has a predetermined break-down voltage. ASo soon as the potential of storage condenser 4, for example, has reached that break-down voltage with respect to ground, gas diode I begins to conduct. The charge which storage condenser 4 receives during the arrival of each pulse I6 depends upon the value of anode supply voltage B+ and the capacitances of charging condenser 20 and storage condenser 4, as is well known in the art. Thus, after one or more predetermined number of pulses I6 the voltage across storage condenser 4 will be sufficient to break down gas diode I. Gas diode I will continue to conduct space current until the voltages on storage condensers 4 and 5 are substantially 4 equal. It is to be understood, of course, that gas diode I will cease to conduct space current when the voltage across storage condenser 4 equals that across storage condenser 5 minus the extinguishing voltage of gas diode I.

After a predetermined number of input pulses I6 the voltage across storage condenser 5 will be sufiicient to break down gas diode 2 whereupon storage condenser 6 begins to charge up in steps through gas diode 2. Finally when storage condenser 6 has reached the break-down voltage, all three gas diodes I, 2 and 3 will conduct space current so that storage condensers 4, 5 and 6 are discharged simultaneously through load resistor I and ground. It will be understood that the count-down ratio of the frequency divider of the invention, that is the ratio of the frequency of input pulses I6 to that of the output pulses obtained from terminals Ill, depends upon the capacitances of condensers 20, 4, 5 and 6. The capacitances of condensers 4, 5 and 6 should increase progressively so that the capacitance of condenser 6 divided by the capacitance of condenser 4 is equal to the count-down ratio provide-i that gas diode I fires each time an input pulse I6 is received. Otherwise the count-down ratio of the frequency of input pulses I6 compared to that of the pulses developed between ground and the output of diode I must be taken into account.

For a count-down ratio of :1 storage condensers 4, 5 and 6 may, for example, have a capacitance of .01, .1 and .6 microfarad, respectively. It may be assumed that every input pulse It will charge storage condenser 4 sufficiently to break down gas diode I. After ten pulses, storage condenser 5 will have a voltage suficient to fire gas diode 2. After sixty pulses the voltage of storage condenser 6 will be sufiicient to fire gas diode 3. In that case diodes I, 2 and 3 conduct space current simultaneously, thus discharging storage condensers 4, 5 and 6 through load resistor 'I and ground. The output pulses at one-sixtieth the frequency of the input pulses appear across load resistor I and may be obtained from output terminals II]. It is to be understood that any number of gas diodes may be connected in series and shunted individually by storage condensers, the number of gas diodes and condensers depending upon the desired count-down ratio. I

Referring now to Fig. 2, in which like components are designated by th same reference numerals as where used in Fix i, there is illustrated a modified frequency d ider circuit. The frequency divider circuit r Fig. 2 again comprises three gas diodes I, 2 and 3 arranged in series and shunted individually by storage condensers 4, 5 and 6. The input pulses are impressed upon the first storage condenser 4 through a half wave rectifier circuit. An alternating current source is connected to terminals 25, and voltage variations are impressed upon primary winding 26 inductively coupled to secondary winding 21 of transformer 28. The input signal may be of sinusoidal form as shown at 30. secondary winding 21 is connected through high vacuum diode 3| to storage condenser 4 and gas diode I. The other terminal of secondary winding 21 is connected to ground through load resistor 32. The pulses appearing across the output of high vacuum diode 3| are illustrated at 33. It will be understood that high vacuum diode 3| is arranged as a half wave rectifier.

The frequency divider circuit of Fig. 2 operates as follows. Each pulse 33 impressed upon storage One terminal of condenser. 4 will charge it to a certain voltage which preferably is equal to the break-down voltage of gas diode l. Accordingly, every time a pulse 33 is impressed upon storage condenser 4 gas diode i fires and storage condenser receives a certain charge. After a predetermined number of steps the voltage of storage condenser 5 has reached the break-down voltage of gas diode 2 which thereupon begins to fire and charge storage condenser 6. Finally storage condenser 6 will reach the break-down voltage of gas diode 3, whereupon all three gas diodes I, 2 and 3 will conduct space current and discharge storage condensers 4, 5 and 6 through load resistance 1.

While there has been described what is at present considered the preferred embodiment of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention, and it is, therefore, aimed in the appended claims to cover all such changes and modifications as fall within the true spirit and scope of the invention.

What is claimed is:

1. A frequency divider circuit comprising a, plurality .of charge storage elements, means for applying pulses to a first one of said elements, means for connecting each of said elements with a succeeding element whenever the preceding element has received a predetermined number of charges, and means for discharging simultaneously all of said elements whenever the last one of said elements has received a predetermined number of charges.

2. A frequency divider circuit comprising a plurality of storage condensers, means for applying spaced pulses across the first one of said condensers, unilaterally conducting devices for connecting each of said condensers with a succeeding condenser whenever the preceding condenser has received a predetermined number of charges, and means including said unilaterally conducting devices for discharging simultaneously all of said condensers whenever the last one of said condensers has received a predetermined number of charges. I

3. A frequency divider circuit comprising a plurality of unilaterally conducting devices of predetermined break-down voltage and connected in se'ries,a source of fixed reference potential, a plurality of storage condensers each being connected between said source of reference potentie] and the input of one of said devices, means for applying spaced pulses of a predetermined voltage across the first storage condenser, the capacitances of said condensers increasing progressively from the first to the last condenser, thereby to render each of said devices conducting when the condenser in its input circuit has reached said break-down voltage with respect to said source of reference potential, and means for deriving output pulses at a submultiple of the frequency of said input pulses.

4. A frequency divider circuit comprising a plurality of gas diodes of predetermined breakdown voltage and connected in series, a source of fixed reference potential, a plurality of storage condensers each being connected between said source of reference potential and the input of one of said diodes, means for applying spaced pulses of a predetermined voltage across the first storage condenser, the capacitances of said condensers increasing progressively from the first to the last condenser, thereby to render each of said diodes conducting when the condenser in its input circuit has reached said break-down voltage with respect to said source of reference potential, and means for deriving output pulses at a sub-multiple of the frequency of said input pulses from the last of said diodes.

5. A frequency divider circuit comprising a plurality of cold cathode gas diodes of predetermined break-down voltage and connected in series, a source of fixed reference potential, 9. plurality of storage condensers each being connected between said source of reference potential and the input of one of said diodes, means for applying spaced pulses of a predetermined voltage across the first storage condenser, the capacitances of said condensers increasing progressively from the first to the last condenser, there by to render each of said diodes conducting when the condenser in its input circuit has reached said break-down voltage with respect to said source of reference potential, and means for deriving output pulses at a submuitiple of the frequency of said input pulses from the last of said diodes.

6. A frequency divider circuit comprising a plurality of unilaterally conducting devices of predetermined break-down voltage and connected in series, a source of fixed reference potential, a

plurality of storage condensers each being connected between said source of reference potential and the input of one of said devices, means for applying spaced pulses of a predetermined voltage across the first storage condenser, the capacitances of said condensers increasing progressively from the first to the last condenser, thereby to render each of said devices conducting when the condenser in its input circuit has reached said break-down voltage with respect to said source of reference potential, and a load impedance connected between said source of reference potential and the last of said devices for deriving output pulses at a submultiple of the frequency of said input pulses.

7. A frequency divider circuit comprising a plurality of gas diodes of predetermined break-down voltage and connected in series, a source of fixed reference potential, a plurality of storage condensers each being connected between said source of reference potential and the input of one of said diodes, means for applying spaced pulses of a predetermined voltage across the first storage condenser, the capacitances of saidcondensers increasing progressively from the first to the last condenser, thereby to render-each .of said diodes conducting when the condenser in its input circuit has reached said break-down voltage with respect to said source of reference potential, and a load impedance connected. between said source of reference potential and the last of said diodes for deriving output pulses at a submultiple of the frequency of said input pulses.

CLYDE E. HALLMARK. REFERENCES CITED The following references are of record in the file of this patent:

UNITED STATES PATENTS 

